This work presents the design, simulation, and layout of a CMOS active pixel sensor (APS) employing a three-transistor (3T) architecture with integrated column-parallel readout. Each pixel consists of a reset switch, source-follower amplifier, and row-select device, interfacing with a photodiode that generates a photocurrent proportional to incident illumination. A current-mode column readout circuit enables robust signal acquisition and biasing. Pixel functionality is validated through transient simulations utilizing modeled photocurrents and bias voltages. Row and column scanning are achieved using custom C²MOS shift registers to facilitate sequential raster readout. A 4×4 pixel array is implemented and laid out within a 2.5 mm × 2.5 mm die area, achieving full DRC and LVS compliance. The design demonstrates high fill factor, low-power operation, and scalability, providing a foundation for future monolithic CMOS imaging systems.

Blue Jay Racing is a team of undergraduate engineers at the Johns Hopkins University. Student team members take part in designing, building, and racing a single seat off-road vehicle against approximately 200 teams representing university engineering programs from 14 nations. The award-winning program, founded in 2004, offers young engineers an educational experience that goes beyond what the classroom can offer. In addition to technical knowledge gained during the design/build process, students also learn critical team-building skills which will be extremely important in the development of each individual’s ability to become leaders in academia and/or industry.

Here we present a novel packaging method for single-dose cough syrup using an interior wax coating to decrease the volume of residual liquid after use. We consider the manufacturing, regulatory, and financial analysis for building a company based on this product.

For our Intro to VLSI final project, my team and I designed a CMOS image sensor using Cadence tools. We built and simulated a 3T active pixel sensor, CMOS row and column shift registers, and column read-out circuits. We laid out a full 4×4 pixel array and verified our design with DRC and LVS checks. The system supports raster scanning, with all control signals driven by our custom shift registers. We fit the full design in a 2.5mm × 2.5mm layout and presented our results at Design Day.