Create

Design Project Gallery

Project Search
Search projects by keyword, program, course, or submission year.

CMOS Imager

Project Description:

This work presents the design, simulation, and layout of a CMOS active pixel sensor (APS) employing a three-transistor (3T) architecture with integrated column-parallel readout. Each pixel consists of a reset switch, source-follower amplifier, and row-select device, interfacing with a photodiode that generates a photocurrent proportional to incident illumination. A current-mode column readout circuit enables robust signal acquisition and biasing. Pixel functionality is validated through transient simulations utilizing modeled photocurrents and bias voltages. Row and column scanning are achieved using custom C²MOS shift registers to facilitate sequential raster readout. A 4×4 pixel array is implemented and laid out within a 2.5 mm × 2.5 mm die area, achieving full DRC and LVS compliance. The design demonstrates high fill factor, low-power operation, and scalability, providing a foundation for future monolithic CMOS imaging systems.

Project Photo:

Layout of a 4×4 CMOS active pixel sensor array with labeled shift registers for row, reset, and column control. The layout spans 50 µm in height and 54 µm in width. Pixels are centrally tiled in a grid, with control logic placed along the left and bottom edges.

Final layout of a 4×4 CMOS active pixel sensor (APS) array with integrated C²MOS shift registers for row, column, and reset control. The design enables sequential raster readout through coordinated scanning logic, supporting low-power and scalable image sensing applications.

Student Team Members

  • Tianai Yue
  • Rudy Zhang
  • Chris Lo

Course Faculty

Project Mentors, Sponsors, and Partners

  • Ralph Etienne-Cumming, JHU ECE