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A Functional Compact and Sensitive CMOS Imager Design
- Program: Electrical and Computer Engineering
- Course: Other
- Year: 2024
Project Description:
A CMOS imager design intended for modern mobile applications composed of an array of active pixel sensors (APS). Design is implemented in Cadence using TSMC 0.18u technology node.
Project Photo:
Overview of a 4×4 APS array for testing purposes