Verilog is a description language that describes the behavior of a logic circuit at gate level. It can also be used for simulation of a logic designs. It does not just simulate the function of the circuit but also the delays for switching each gate.

The first step in running a Verilog simulation is to create the behavioral files for each gate that you wish to simulate. From the schematic file you can then run the simulation of the total design you have created. The last step is to evaluate the results from the input and output waveforms in a program called SimVision