We’ll now create a Verilog description of the inverter. In your library manager click once on the digital_lib library and then click once on the inv cell view. Now left click Library manager:File->New Cellview. In the dialog box type behavioral in the View Name field. Select Verilog-Editor for the Tool. Make sure that you inv is selected in the Cell category and digital_lib is selected in the Library field.

Left click OK. The text tool should now appear, with some basic template stuff inside. Anything preceded by a “//” is considered to be a comment. So, after the comment line, make the file look like this:

module inv(in, out, vdd, vss);

    inout in;   
    inout vdd;  
    inout vss;  
    inout out;  

    not #2 n1(out, in);    

endmodule   

This is all the text you need in order to describe your inverter. Now you can save the text file and you are ready to simulate the behavioral model. The commands that you used in the text file are describe bellow.

• module - defines the beginning of a Verilog module.
• inv(...) - Specifies the name of the module. All pins (connections to the outside world) must be specified inside the parenthesis.
• inout - Defines what the input/output pins into the module are.
• not - tells that this gate is an inverter. There are three basic gates: NOT, NAND, and NOR.
• #2 - gives the propagation delay of the gate (in nanoseconds - in our case). For instance, #2 signifies a 2ns delay through the gate.
• n1(...) - A module may consist of several different gates. Therefore, each gate must have a number. All inputs & outputs to that particular gate must be listed inside the parenthesis, but the outputs are specified first.
• endmodule - signifies the end of this particular module.