This manual is intended primarily for students enrolled in Intro to VLSI, CAD for Digital VLSI, or Mixed-Mode VLSI offered at The Johns Hopkins University. Basic knowledge of how CMOS transistors operate is required. The main goal of this manual is to teach you to use the Cadence Design Environment to design and test digital CMOS circuits. This manual will walk you through all the necessary steps for designing and testing an inverter using the NSCU toolkit. First, we are going to create a schematic for the inverter. We, then, create a symbol for the inverter and test the transient and DC characteristics of this inverter using Analog Artist Simulator. Next, we are going to create a layout for the inverter and test the transient and DC characteristics on the layout of the inverter. Finally, we are going to create a behavioral view for the inverter in Verilog XL and simulate its behavior.
- Conventions Used in this manual
- Starting the Cadence software
- Opening and Using the Library Manager
- Design Hierarchy
- Quitting the Session
- Creating a new library
- Creating a new Cell: Inverter
- Creating Symbols: Inverter Symbol
- Schematic Simulation: Creating a Test File for a Simulating an Inverter
- Spice simulation: DC Analysis of The Inverter
- Schematic Simulation: Transient Analyses of The Inverter
- Layout: Creating Layout for an Inverter
- Design Rule Check (DRC)
- Layout Extraction
- Layout Versus Schematic (LVS)
- Layout Simulation: Transient Analysis
- Another method for Layout Simulation
- Verilog Hardware Description Language
- Creating a Behavioral Model for an Inverter
- Verilog Simulation
“Information is provided “as is” without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk - and any attempt to use this information is at your own risk - we recommend using it on a copy of your data to be sure you understand what it does and under what conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment.”
Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134