Courses

520-142 Digital Systems Fundamentals                             Spring 2015

Time: Monday, Wednesday, Friday, 11 a.m, Hackerman Hall, Room B17

Instructor: Dr. G. Meyer, Barton Hall, Room 310, e-mail: [email protected]
Teaching Assistant:
Eshan VARIANI: Barton Hall, Room 218, :  Cell: 410-336-9049
Congyuan (Cy) YANG: Barton Hall, Room 218, Cell: 410-736-1253

booksRecommended Text: Digital Logic,Circuit Analysis and Design, V.P. Nelson, H.T. Nagle, J. D. Irwin, B. D. Carroll, Prentice Hall.

 

 

 

Hand out: Problems for Digital System Fundamentals, Version 24.
Hand out: Lab 1: Introduction to the Training Kit and Basic Gates, and Lab 2: Combinational Logic Circuits

Office Hours:
G. Meyer : Monday 10-11, Tuesday 10-11
Eshan VARIANI: Tuesday 9-11, Thursday 9-11, Friday 9-11
Congyuan (Cy) YANG: Monday 9-11, Wednesday 9-11, Thursday 12-2
Educational Objectives: Development of the ability to analyze and synthesize combinational and synchronous sequential logic circuits

Grading: HomeWork 10%, Midterm 1 15%, Midterm 2 30%, Final 45%

Laboratory Session 1: Friday, March 13, 2015, Hackerman 224

Laboratory Session 2: Monday, March 23, 2015, Hackerman 224

Midterm 1: Location: Hackerman Hall Room B17, Wednesday, March 4, 2015 Max:  , Low:  , Average: , Standard Deviation:

Midterm 2: Location: Hackerman Hall Room B17, Monday, April 6, 2015 Max: , Low: , Average: , Standard deviation:

Final: Location: Hackerman Hall Room B17, Date: Tuesday, May 12, 2015, Time: 9 am Max: , Low: , Average: , Standard deviation:

Note: Homeworks and midterms not picked up in class may be obtained from the teaching assistants

Note: Any student with a disability who may need accommodations in this class must obtain an accommodation letter from Student Disability Services, 385 Garland, (410 516-4720, [email protected]