Designing a complete MS CMOS-based system for image pre-processing, segmentation, tracking, and classification.
With the volume of visual sensor data increasing exponentially, there is a dramatic increase in the complexity of analysis, reflected in the number of operation per pixel per second. This project involves designing a complete MS CMOS-based system for image pre-processing, segmentation, tracking, and classification. In doing so, we utilize the IFAT (Integrate and Fire Transceiver) model and ideas for computing various image processing functions. It is a mixed-signal VLSI model of a capacitor array representing an array of I&F neurons which integrate and spike using AER communication to send/receive spikes/events. The idea of using this biologically-plausible analog-VLSI approach for visual processing is ideal for processing speed and power efficiency. Furthermore, we apply unconventional Bayesian Approximation and Inference algorithms which use stochastic computation to also allow for a large reduction in amount of data required for accurate computations. We can further apply these ideas to numerous other vision-related applications.